Stacked CSP

Model Number

LF-BGA

Amkor's Stacked CSP packages leverage existing CABGA manufacturing capabilities and proven package infrastructure while adding the enhancement of placing one die on top of another.

Stacked CSP packages combine the use of thin core substrate material, wafer backgrinding know-how (to 7 mils), and conventional BGA surface mount techniques to offer double the memory capacity for increased device functionality while allowing manufacturers to maintain size reduction roadmaps. This technology allows for very efficient use of mother-board real estate, reducing size and weight and supporting the customer's system level cost reduction needs. Stacked CSPs also offer the user the flexibility of combining custom memory with off- the-shelf devices to further reduce total systems cost.

Applications

Stacked CSP packages are designed for products requiring increased memory density and performance while reducing package size. Portable electronics products such as cell phones, PDAs, camcorders and other wireless consumer systems can benefit from the combination of stacked die and small footprint offered by Amkor's Stacked CSP.

Features

• 8 - 15 mm Body size
• BGA package height at 1.2 and 1.0 mm max
• Four key assembly technologies to accommodate thinner 1.4, 1.2 & 1.0 mm profiles, 3 + die Die stack-ups and proliferation of die stacking across all package platforms
• Flash / SRAM combination with up to 80 I/O
• 16- and 32-Mbit Flash densities combined with 2-and 4-Mbit SRAM
• Logic / Flash, Digital / Analog and other ASIC / Memory combinations of 320 I/O and greater
• Established package infrastructure with standard CABGA footprints
• Consistent product performance and reliability
• JEDEC Standard Outlines including MO-192 and MO-219
• Thin spacer technology
• Die overhang wire bonding
• Low loop wire bonding less than 100 µm
• Wafer thinning / handling to 75 and 50 µm

Amkor assures a reliable performance by continuously monitoring key indices:

• Moisture Resistance Testing: JEDEC Level 3 @ 260°C
• Additional Test Data at: [ (30°C / 85% RH / 96hrs) + 260 ] x2 or 3
• Unbiased Autoclave/PCT: 121°C / 100% RH / 2atm, 168 hours
• Temp / Humidity: 85°C / 85% RH / 1000 hours
• High temp storage: 150°C, 1000 hours
• Temp cycle: -55 / +125°C, 1000 cycles

• Thermal cycle: -40 / +125°C, 4000 cycles

• Die qty, stack: 2 and 3+ die configurations
• Ball pad pitch: 0.5, 0.65, 0.75, 0.8 mm
• Die thickness (min): 150µm (6 mils)
• Laminate core thickness: 100 or 150 µm
• Ball diameter: 0.3, 0.4, 0.46 mm
• Die bond pitch (min): 65 µm (In-line)
• Wirebond length (max): 5 mm (200 mils)
• Wirebond dia (min): 20, 25, 30 µm
• Wafer backgrinding: Standard

• Package Substrate
  - Layer count (Laminate): 2-4
  - Dielectric: Laminate (e.g., E679, BT) Polyimide (e.g., Kapton®)
• Device type: Silicon, SiGe, etc.
• Die attach
  - (Bottom die): Silver Filled Epoxy
  - (Top die): Non-conductive Epoxy or Elastomeric Film
• Wire type, Gold: High tensile
• Encapsulant: Liquid Epoxy (Black)
• Solderball: 63Sn / 37Pb & PbFree Sn/3-4Ag / 0.5Cu
• Marking: Laser

Daisy Chain Availability (mm)

S-CSP Designation	2 Die	2 + 1
Package Body Size	8 x (10, 12, 14) mm	15 x 15 mm
I/O Count	72 (64 + 8)	208 (P4)
Ball Pitch	0.8 mm	0.8 mm
Top Die	2.54 x 7.62 mm	3.8 x 7.6 mm
Bottom Die	5.05 x 6.88 mm	7.6 x 7.6 mm
Side Die	N/A	5.1 x 5.1 mm
Package Thickness (max)	1.4 mm	1.4 mm
Substrate	2 layer	2 layer